From Incentives to Intangibles: Semiconductor Layout-Design Protection under the SICLD Act, 2000
Introduction : India’s semiconductor policy has moved beyond the language of aspiration into physical production. In September 2026, the Ministry of Electronics and Information Technology reported that five semiconductor manufacturing plants had commenced commercial production, while the next phase of policy was being directed towards design, materials, fabrication, advanced packaging, research and talent. That development makes an older part of India’s intellectual property architecture newly consequential, the Semiconductor Integrated Circuits Layout-Design Act, 2000 (SICLD Act). The question is whether that statute remains usable, precise and institutionally aligned with the semiconductor ecosystem now being built.
The policy premise also needs one legal clarification. The principal semiconductor manufacturing incentives are not a conventional production-linked incentive scheme. The Union Cabinet’s 2021 Programme for Development of Semiconductors and Display Manufacturing Ecosystem, later modified in 2022, created substantial fiscal support for fabs and packaging facilities, including support of 50% of project cost for silicon semiconductor fabs and 50% of capital expenditure for specified compound semiconductor and ATMP/OSAT facilities. Alongside that manufacturing support sits the Design Linked Incentive scheme, and, from 2026, India Semiconductor Mission 2.0, which expressly emphasises full-stack Indian semiconductor IP, equipment and materials, research and training. The policy trajectory links capital-intensive manufacturing with domestic ownership of design capabilities. That is where the Semiconductor Integrated Circuits Layout-Design Act, 2000 (SICLD Act) must be examined.
The statute is specialised by design
The SICLD Act was enacted to give effect to India’s obligations under the TRIPS Agreement concerning integrated-circuit layout designs. Its subject matter is narrower than the semiconductor industry as a whole. Section 2(h) defines a layout-design through the arrangement of transistors and other circuitry elements, including connecting lead wires, as expressed in a semiconductor integrated circuit. The law protects a particular form of intellectual effort, the topographical organisation of a chip, rather than the underlying scientific principle, the commercial product incorporating the chip, or its brand. This matters because semiconductor value is distributed across several layers of innovation and different IP rights attach to each layer.
The eligibility test is deliberately lighter than patent law but demanding in another respect. Section 7 requires the layout-design to be original, inherently distinctive and capable of being distinguished from another registered layout-design, while excluding designs already commercially exploited, subject to the Act’s limited two-year treatment of such exploitation. This reflects the rationale of sui generis protection. Chip topographies may require extensive engineering effort and investment even though their creation does not neatly correspond to the inventive-step model of patent law. WIPO similarly identifies layout-design protection as a distinct system developed because copying a completed topography can be considerably cheaper than creating it.
The regime remains conceptually sound. Its weakness emerges when the formal right is tested against a modern design-to-fabrication workflow.
Protection exists, but the transaction costs of using it matter
Registration is central to the Indian model. Applicants must provide the prescribed representation of the layout-design, and the Registry’s current guidance contemplates drawings or photographs of the mask layout and, where applicable, and process-design-kit information. A registration system must permit the authority to identify the protected topography without forcing disclosure of commercially sensitive process information that lies outside the legal subject matter.
The term of protection is ten years, calculated from the filing date or first commercial exploitation, whichever is earlier. This satisfies the minimum duration contemplated by TRIPS. The Act gives the registered proprietor an exclusive right to use the layout-design, and infringement covers reproduction and commercial importation, sale or distribution of the protected layout-design or a semiconductor circuit incorporating it. The structure therefore targets direct copying while recognising that the protected object may be embodied in a commercial article.
Yet formal breadth should not be confused with practical coverage. The IP India annual report recorded only thirty-one applications filed by 31 March 2025, of which seven had been registered and eight had been rejected or abandoned after examination. Those figures do not prove inadequacy, but they show that registration has not become routine in India’s semiconductor innovation system. In an industry where policy is now seeking to attract fabrication, packaging and indigenous chip design at scale, low utilisation of the dedicated topography registry is a relevant institutional signal.
TRIPS compliance is the floor, not the whole test
On core rights, the Indian regime tracks the international baseline closely. TRIPS Article 35 incorporates substantial elements of the Washington Treaty framework, Article 36 requires protection against specified commercial acts, Article 37 addresses innocent acquisition and non-voluntary use, and Article 38 requires at least ten years of protection in registration-based systems. India’s infringement provisions similarly accommodate an innocent commercial actor who lacked knowledge, while imposing a royalty consequence after notice in defined circumstances. The statutory architecture is therefore not deficient merely because it is sui generis or differs from patent law.
The more difficult question concerns non-voluntary use. The Act permits the Appellate Board, on a government application, to authorise use of a registered layout-design for purposes such as a national emergency, extreme public urgency, public non-commercial use or to remedy anti-competitive conduct, subject to conditions and royalty. It also ordinarily requires prior efforts to obtain authorisation on reasonable commercial terms. This is broadly consistent with the TRIPS treatment of compulsory or government use of layout-designs. The provision matters because semiconductor technology may support defence, communications and critical infrastructure, where supply disruption can extend beyond an ordinary commercial dispute.
However, the institutional design is less settled than the substantive rule. Section 51 still assigns public-use authorisation to the Appellate Board, making the forum for urgent non-voluntary use less clear than the substantive grounds for authorisation. The post-tribunal judicial system has nevertheless begun to absorb SICLD proceedings, the Delhi High Court’s Intellectual Property Division rules expressly provide forms for proceedings under sections 40 to 42, including appeals under section 42. This shows judicial adaptation, but the statutory text has not been comprehensively modernised.
Recalibrating the regime for an Indian semiconductor ecosystem
India does not need to replace the SICLD Act simply because manufacturing has expanded. Its architecture remains appropriate, specialised rights, registration-based certainty, protection against copying, and safeguards for public and research uses. The more pressing need is integration.
First, the SICLD Registry should be treated as part of semiconductor industrial policy rather than as an isolated IP office. Registration assistance, model filing guidance and IP counselling should be incorporated into design-support programmes rather than left to creators after commercialisation begins.
Second, the disclosure architecture deserves refinement. The objective should be to make the protected topography identifiable and enforceable without unnecessarily exposing confidential fabrication know-how. Rules and registry practice should clearly distinguish layout information from broader manufacturing know-how.
Third, the non-voluntary-use framework should be institutionally consolidated. A right that is subject to public-interest authorisation must have a plainly identifiable forum, procedure, timelines and review mechanism. High Court IP Divisions now provide a workable judicial setting, but the legislation should expressly reflect that institutional reality rather than leaving important functions tied to obsolete tribunal language.
Finally, adequacy should be measured not only against TRIPS but against actual innovation behaviour. India’s current semiconductor push makes that distinction harder to ignore. When fabs, packaging units and indigenous chip design are being supported simultaneously, the value of a layout-design right lies in whether designers can obtain it predictably, transact around it confidently and enforce it when copying occurs.
Conclusion
The SICLD Act, 2000 is not obsolete because it predates India’s present semiconductor expansion. Its sui generis logic remains consistent with chip innovation, and its principal rights substantially meet the TRIPS baseline. The problem is fit. A regime with few registrations, legacy appellate references and a much smaller original domestic base needs procedural and administrative recalibration.
India’s next semiconductor phase therefore requires more than incentivising physical production; its intangible architecture must function with equal precision. The SICLD Act can supply that foundation, but only if registration, confidentiality, enforcement, public-interest use and design-support policy are treated as parts of one semiconductor innovation system rather than as separate legal compartments.
Author: Amrita Pradhan in case of any queries please contact/write back to us via email to content@khuranaandkhurana.com or at Khurana & Khurana, Advocates and IP Attorney
References
Ministry of Electronics & Information Technology, ‘Precision Manufacturing Ecosystem Emerging as Key Enabler for India’s Semiconductor Industry’ (Press Information Bureau, 18 September 2026) https://www.pib.gov.in/PressReleasePage.aspx?PRID=2312207
Ministry of Electronics & Information Technology, ‘India Semiconductor Mission 2.0: A Major Push in Budget 2026 towards Semiconductor Self-Reliance’ (Press Information Bureau, 7 February 2026) https://www.pib.gov.in/PressReleasePage.aspx?PRID=2224839
Ministry of Electronics & Information Technology, ‘Promotion of Make in India in Electronics and Information Technology Sector’ (Press Information Bureau, 16 December 2022) https://www.pib.gov.in/PressReleasePage.aspx?PRID=1884069
World Intellectual Property Organization, ‘Patent Expert Issues: Layout Designs (Topographies) of Integrated Circuits’ (WIPO) https://www.wipo.int/en/web/patents/topics/integrated_circuits
Office of the Controller General of Patents, Designs & Trade Marks, ‘Semiconductor Integrated Circuits Layout-Design Registry: FAQs’, questions 6 and 12 https://ipindia.gov.in/sicldr-faqs
Office of the Controller General of Patents, Designs, Trademarks and Geographical Indications, Annual Report 2024-25 (Chapter X, Semiconductor Integrated Circuits Layout Design Registry) 94-95.
World Trade Organization, Agreement on Trade-Related Aspects of Intellectual Property Rights, arts 35-38 https://www.wto.org/english/docs_e/legal_e/trips_e.htm
Delhi High Court, Intellectual Property Rights Division Rules 2021, forms under ss 40 and 42 of the Semiconductor Integrated Circuits Layout-Design Act 2000 https://delhihighcourt.nic.in/web/sites/default/files/Notifications%20and%20Practice%20Directions/notificationfile_wd6kndkfb4g.pdf
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